1. Field of the Invention
The invention relates to the field of semiconductor device fabrication techniques and more particularly to the field of fabrication techniques for the fabrication of very large scale integrated circuits (VLSI) having increased density and reliability and containing FET devices, polysilicon and diffused N+ interconnect lines, and metallized interconnect lines interfacing with the polysilicon and N+ diffused lines.
2. Prior Art
The semiconductor art has been concerned with reducing the size and power consumption of individual devices and intergrated circuits in order to increase the logic power of these circuits per unit area. A particular effort has been extended in the area of monolithic random access memories (RAM's) and read only memories (ROM's) having very large memory capacity. Many things have been done over the years in an attempt to reduce the size of devices and improve tolerances with which they are fabricated. Such efforts have included, inter alia, fine line lithography, improved mask generation and alignment machines, improved tolerances on mask alignment, and self-aligned gates. These techniques have reduced the area required for the fabrication of the individual FET devices used in these integrated circuits. However, because of alignment tolerances, the FET devices must be designed with larger geometry than they would have to be if perfect mask alignment were obtained. Furthermore, because of alignment tolerances, the FET devices must be spaced further apart than otherwise necessary in order to allow for the misalignment in the formation of the interconnection lines. Consequently, there is a need for an improved integrated circuit fabrication technique for producing VLSI circuits including FET devices and conducting lines having reduced sensitivity to mask alignment.